Recent electronic apparatuses such as personal digital assistants (PDAs) and so on are equipped with devices requiring a power source voltage higher or lower than a battery voltage. A step-up, step-down or step-up/step-down type switching regulator is used to supply a proper power source voltage to such devices.
FIG. 1 is a circuit diagram showing a switching regulator 4r. The switching regulator 4r includes a control circuit 100r and an output circuit 102. The output circuit 102 includes a switching transistor M1, a synchronous rectifying transistor M2, an inductor L1 and an output capacitor C and has a topology of a step-down type switching regulator. The control circuit 100r switches the switching transistor M1 and the synchronous rectifying transistor M2 to stabilize an output voltage VOUT to a target value.
The control circuit 100r includes a bottom detection comparator 10, a driving circuit 20r, an off signal generator 50 and a zero current detector 60 in order to stabilize the output voltage for a light load. A first voltage-dividing resistor R1 and a second voltage-dividing resistor R2 divide the output voltage VOUT to generate a feedback voltage VFB based on the output voltage VOUT. The bottom detection comparator 10 compares the feedback voltage VFB with a predetermined reference voltage VREF and generates an on signal SON asserted (for example, having a high level) when the feedback voltage VFB decreases to the reference voltage VREF.
The off signal generator 50 includes a current detector 52 and a peak current detection comparator 54 and asserts an off signal SOFF when current IM1 flowing into the switching transistor M1 reaches a predetermined peak current IPEAK.
In an on period of the switching transistor M1, a voltage VLX of a junction point (a switching terminal LX) of the switching transistor M1 and the synchronous rectifying transistor M2 is given by VDD-IM1×RON1. Where, RON1 denotes an on resistor of the switching transistor M1. The current detector 52 generates a detection voltage VIM1 depending on a voltage drop (IM1×RON1) of the switching transistor M1.
The peak current detection comparator 54 compares the detection voltage VIM1 with a threshold voltage VPEAK corresponding to the peak current IPEAK and asserts the off signal SOFF (for example, having a high level) when the detection voltage VIM1 reaches the threshold voltage VPEAK, in other words, when the current IM1 reaches the predetermined peak current IPEAK.
The zero current detector 60 asserts a zero current detection signal SZERO when current IM2 flowing into the synchronous rectifying transistor M2 decreases to a near-zero threshold value IZERO. In an on period of the synchronous rectifying transistor M2, a voltage VLX of the switching terminal LX is given by VIM2=−RON2×IM2. Where, RON2 denotes an on resistor of the synchronous rectifying transistor M2. The zero current detector 60 includes a comparator to compare the voltage VLX of the switching terminal LX with a predetermined threshold voltage VZERO.
The driving circuit 20r includes a control logic part 22r and a pre-driver 24. The control logic part 22r receives the on signal SON, the off signal SOFF and the zero current detection signal SZERO and generates a control signal to direct turning-on/off of the switching transistor M1 and the synchronous rectifying transistor M2. The pre-driver 24 controls the switching transistor M1 and the synchronous rectifying transistor M2 based on the control signal generated by the control logic part 22r. 
When the on signal SON is asserted, the driving circuit 20r turns on the switching transistor M1 and turns off the synchronous rectifying transistor M2 (a first state φ1). Subsequently, when the off signal SOFF is asserted, the driving circuit 20r turns off the switching transistor Ml and turns on the synchronous rectifying transistor M2 (a second state φ2). Subsequently, when the zero current detection signal SZERO is asserted, the driving circuit 20r turns off both of the switching transistor M1 and the synchronous rectifying transistor M2 (a third state φ3).
FIGS. 2A and 2B are operation waveform diagrams of the switching regulator 4r of FIG. 1. Prior to time t1, the switching regulator 4r is in the third state φ3 and the switching transistor M1 and the synchronous rectifying transistor M2 are in a turned-off state. The output capacitor C1 is discharged by load current and the output voltage VOUT is decreasing. At time t1, when the feedback voltage VFB decreases to the reference voltage VREF, the on signal SON is asserted. Due to this assertion, the switching regulator 4r transitions from the third state φ3 to the first state φ1 and the switching transistor M1 is turned on.
When the switching transistor M1 is turned on, the voltage VLX of the switching terminal LX rises to the proximity of an input voltage VDD. In addition, as coil current LCOIL increases, i.e., as the current LM1 of the switching transistor M1 increases, a voltage drop of the switching transistor M1 increases and the voltage VLX of the switching terminal LX is lowered.
At time t2, when the voltage drop of the switching transistor M1 reaches the threshold value VPEAK, in other words, when the voltage VLX of the switching terminal LX decreases to VDD-VPEAK, the off signal generator 50 asserts the off signal SOFF. Due to this assertion, the switching regulator 4r transitions from the first state φ1 to the second state φ2, the switching transistor M1 is turned off and the synchronous rectifying transistor M2 is turned on.
At time t3, when current flowing into the synchronous rectifying transistor M2 decreases to the near-zero threshold value IZERO, the zero current detection signal SZERO is asserted. Due to this assertion, the switching regulator 4r transitions from the second state φ2 to the third state φ3, both of the switching transistor M1 and the synchronous rectifying transistor M2 are turned off.
At time t4, when the feedback voltage VFB decreases to the reference voltage VREF again, the on signal SON is asserted and the switching regulator 4r returns to the first state φ1. The switching regulator 4r repeats the first to third states φ1 to φ3 in a light load state.
The switching regulator 4r of FIG. 1 has the following problems. The bottom detection comparator 10 has a response delay τD which has an effect on the output voltage VOUT. The effect of the response delay τD on the output voltage VOUT will now be described with reference to FIG. 2B.
In FIG. 2B, a solid line represents an ideal state where a response delay is zero. With the zero response delay, when the feedback voltage VFB decreases to the reference voltage VREF, the on signal SON is immediately asserted and the switching regulator 4r transitions to the first state φ1.
When the switching transistor M1 is turned on in the first state φ1, the output capacitor C1 is charged by the coil current LCOIL flowing into the inductor L1 and the output voltage VOUT (the feedback voltage VFB) rises.
In FIG. 2B, an alternating long and short dash line represents a case where a non-zero response delay τD exists. During the response delay τD, since the switching transistor M1 is not turned on, the output voltage VOUT continues to decrease. That is, a ripple (drop amount) of the output voltage VOUT increases as the response delay τD gets longer.
Similarly, a response delay of the peak current detection comparator 54 has an effect on a peak current IPEAK of the coil current ICOIL. When the peak current IPEAK is varied, charges supplied into the output capacitor C1 are varied and the ripple of the output voltage VOUT is also varied.
In order to reduce the ripple of the output voltage VOUT and suppress variation of the ripple, there is a need to increase a response speed of the bottom detection comparator 10 or the peak current detection comparator 54. However, this requires an increase in operation current (bias current) of the bottom detection comparator 10r or the peak current detection comparator 54, which may result in low efficiency of the switching regulator 4r, particularly in a light load state.